1. Field of the Invention
The present invention relates to a digital controlled oscillation circuit using a digital delay circuit and to a PLL circuit using the same.
2. Description of the Related Art
Oscillators used in PLL (phase locked loop) circuits etc. are required to have the characteristics of a smooth transition of frequency by a control signal and a wide oscillation frequency range. Further, there must be no jitter due to changes in the control signal.
For this reason, almost all of the oscillators used in the circuits of the prior art are voltage controlled oscillators (VCO) which control the oscillation frequency by a voltage signal, that is, an analog value.
In the case of a digital PLL circuit, a so-called digital controlled oscillator (DCO) enabling direct controlling of the oscillation frequency of the oscillator by a digital signal has been used.
FIG. 14 shows an example of a PLL circuit using a digital controlled oscillator (hereinafter simply referred to as a DCO).
As shown in FIG. 14, the PLL circuit 1 of the present example is constituted by a phase comparator 2, a digital counter 3, and a DCO 4.
The phase comparator 2 compares the phases of a reference signal S.sub.ref input from the outside and an oscillation signal S.sub.0 from the DCO 4, generates an up signal S.sub.up or a down signal S.sub.dW in accordance with the result of comparison, and outputs the same to the digital counter 3.
The digital counter 3 receives the up signal S.sub.up or down signal S.sub.dw from the phase comparator 2, generates for example an n-bit count value S.sub.C in accordance with the level of these signals, and outputs the same to the DCO 4.
The DCO 4 receives the count value S.sub.C from the digital counter 3, sets the oscillation frequency in accordance with this, generates an oscillation signal S.sub.o of the set frequency, and outputs the same to the phase comparator 2.
In the PLL circuit 1 shown in FIG. 14, the phase comparator 2 compares the phases of the reference signal S.sub.ref input from the outside and the oscillation signal S.sub.C generated from the DCO 4, generates an up signal S.sub.up or down signal S.sub.dw in accordance with the result of comparison, and outputs the same to the digital counter 3. The digital counter 3 generates an n-bit count value S.sub.C. The count value S.sub.C is fed back to the DCO 4, and the oscillation frequency of the DCO 4 is controlled in accordance with this.
Accordingly, the phase of the oscillation signal S.sub.C generated by the DCO 4 follows the phase of the reference signal S.sub.ref input to the phase comparator 2.
As explained above, in the same way as the PLL circuit using the voltage controlled oscillator (VCO) of the related art, an oscillation signal following the phase of the input reference signal can be generated by a PLL circuit provided with the digital controlled oscillator (DCO) shown in FIG. 14.
Below, the configuration and operation of a generally used DCO will be simply explained by referring to FIG. 15 to FIG. 17.
FIG. 15 is a circuit diagram showing an example of a DCO constituted by using a plurality of delay elements imparting different delay times and selectors imparting inverted outputs.
As shown in FIG. 15, the DCO of the present example is constituted by connecting for example n number of delay stages constituted by delay elements D.sub.i (i=n-1, n-2, . . . , 2, 1, 0) and selectors SEL.sub.i in series.
Note that, here, n is an even number.
As illustrated, in the DCO of the present example, one input terminal A of the selector SEL.sub.i constituting each delay stage is connected to an output terminal of the selector of the former stage, while the other input terminal B is connected to the output terminal of the delay element D.sub.i. The input terminal of the delay element D.sub.i is connected to the output terminal of the selector of the former stage.
Note that, the input terminal A of the selector SEL.sub.n-1 of an initial stage is connected to the output terminal of a NAND gate NGT, while the input terminal B is connected to the output terminal of the NAND gate NGT via the delay element D.sub.n-1.
Further, the output terminal of the selector SEL.sub.0 of a final stage is connected to one input terminal of the NAND gate NGT, while an enable signal ENB is input to the other input terminal of the NAND gate NGT.
Further, the output terminal of the NAND gate NGT is connected to the output terminal T.sub.out of the oscillation signal S.sub.0 via an inverter INV.
Bit data C.sub.n-1, C.sub.n-2, . . . , C.sub.2, C.sub.1, and C.sub.0 of for example an n-bit count value SC are respectively input to the selected signal input terminals CK of the selectors SEL.sub.n-1, SEL.sub.n-2, . . . , SEL.sub.2, SEL.sub.1, and SEL.sub.0. Each selector selects the signal of the input terminal A or the input terminal B in accordance with the level of the signal input to the selected signal input terminal and outputs the inverted signal thereof.
For example, when a signal of a low level is input to the selected signal input terminal CK, the selector selects the signal input to the input terminal A, inverts this, and outputs the same to the output terminal. Conversely, when a signal of a high level is input to the selected signal input terminal CK, the selector selects the signal input to the input terminal B, inverts this, and outputs the same to the output terminal.
Further, when assuming that the delay time of a delay element D.sub.0 is T.sub.D, the delay time of the delay element D.sub.i becomes 2.sup.i T.sub.D. For example, the delay time of the delay element D.sub.n-1 becomes 2.sup.n-1 T.sub.D, and the delay time of a delay element D.sub.1 becomes 2T.sub.D.
By the above DCO, the delay time of the signal from the output terminal of the NAND gate NGT to the output terminal of the selector SELO of the final stage is set in accordance with the level of the bit data C.sub.n-1, C.sub.n-2, . . . , C.sub.2, C.sub.1, and C.sub.0 of the count value S.sub.C. When an enable signal ENB of a high level is input to the NAND gate NGT, a ring oscillator is constituted by the delay stages and the NAND gate NGT and oscillates with the oscillation frequency controlled by the count value S.sub.C.
FIG. 16 is a circuit diagram showing an example of the configuration of another DCO.
As shown in FIG. 16, the DCO of the present example is constituted by the NAND gate NGT and n number of delay elements DLY.sub.n-1, DLY.sub.N-2, . . . , DLY.sub.N-2, DLY.sub.N-1, and DLY.sub.0 connected in series and the output terminal of the delay element DLY.sub.0 is connected to the input terminal of the NAND gate NGT, whereby a ring oscillator is constituted.
Note that, here, n is an even number in the same way as the above example.
The delay elements DLY.sub.n-1, DLY.sub.n-2, . . . , DLY.sub.2 DLY.sub.1, and DLY.sub.0 have a similar configuration. FIG. 17 shows the configuration thereof taking the delay element DLY.sub.0 as an example.
As illustrated, the delay element DLY.sub.0 is constituted by nMOS transistors Tn.sub.n-1, Tn.sub.n-2, . . . , Tn.sub.n-2, Tn.sub.n-1, Tn.sub.0, and Tn.sub.00 and pMOS transistors Tp.sub.n-1, Tp.sub.n-2, . . . , Tp.sub.n-2, Tp.sub.n-1, Tp.sub.0, and Tp.sub.00.
The pMOS transistors Tp.sub.n-1, Tp.sub.n-2, . . . , TP.sub.2, Tp.sub.1, and Tp.sub.0 are connected in parallel between the supply line of the power supply voltage V.sub.cc and a node NDp. Namely, sources of the pMOS transistors Tp.sub.n-1, Tp.sub.n-2, . . . , Tp.sub.2, Tp.sub.1, and Tp.sub.0 are connected to the supply line of the power supply voltage V.sub.cc, and drains are connected to a node NDp. Further, inverted signals /C.sub.n-1, /Cn.sub.n-2, . . . , /C.sub.2, /C.sub.1, and /C.sub.0 of the bit data C.sub.n-1, C.sub.n-2, . . . , C.sub.2, C.sub.1, and C.sub.0 of the count value S.sub.C are input to gates of these pMOS transistors.
The source of the pMOS transistor Tp.sub.00 is connected to the node NDp, and the drain is connected to the output terminal T.sub.out.
The nMOS transistors Tn.sub.n-1, Tn.sub.n-2, . . . , Tn.sub.2, Tn.sub.1, and Tn.sub.0 are connected in parallel between the supply line of the ground voltage GND and the node NDn. Namely, sources of the nMOS transistors Tn.sub.n-1, Tn.sub.n-2, . . . , Tn.sub.2, Tn.sub.1, and Tn.sub.0 are connected to the supply line of the ground voltage GND, and drains are connected to the node NDn. Further, bit data C.sub.n-1, C.sub.n-2, . . . , C.sub.2, C.sub.1, and C.sub.0 of the count value S.sub.C are input to gates of these nMOS transistors.
The drain of the nMOS transistor Tn.sub.00 is connected to the output terminal T.sub.ts and the source is connected to the node NDn.
Namely, the drain of the nMOS transistor Tn.sub.00 and the drain of the pMOS transistor Tp.sub.00 are commonly connected to the output terminal T.sub.out of the delay element. Further, the gate of the nMOS transistor Tn.sub.00 and the gate of the pMOS transistor Tp.sub.00 are commonly connected to the input terminal T.sub.in.
In the delay element shown in FIG. 16, the nMOS transistor Tn.sub.00 and the pMOS transistor Tp.sub.00 act as drive use transistors.
The conductive states of the pMOS transistors Tp.sub.n-1, Tp.sub.n-2, . . . , Tp.sub.2, Tp.sub.1, and Tp.sub.0 and the nMOS transistors Tn.sub.n-1, Tn.sub.n-2, . . . , Tn.sub.2, Tn.sub.1, and Tn.sub.0 are set in accordance with the levels of the bit data C.sub.n-1, C.sub.n-2, . . . , C.sub.2, C.sub.1, and C.sub.0 of the count value S.sub.C.
Further, the transistors are set so that they respectively differ in size, for example, the channel widths, therefore, in accordance with the on/off state of each transistor, for example, the ratio of a resistance value between the supply line of the power supply voltage V.sub.cc and the node NDp and the resistance value of the drive use pMOS transistor Tp.sub.00 changes. Similarly, the ratio of the resistance value between the ground line and the node NDn and the resistance value of the drive use nMOS transistor Tn.sub.00 changes. Therefore, the delay time until the inverted signal of the signal input to the input terminal T.sub.in is output to the output terminal T.sub.out is controlled in accordance with the change of this resistance ratio.
Namely, the delay time of the delay elements DLY.sub.n-1, DLY.sub.n-2, . . . , DLY.sub.2, DLY.sub.1, and DLY.sub.0 is controlled by the count value S.sub.C input to the delay elements.
For this reason, when an enable signal ENB of a high level is input to the NAND gate NGT, a ring oscillator is constituted by the delay elements and NAND gate NGT and oscillates with an oscillation frequency controlled by the count value S.sub.C.
However, the above DCOs each have their own disadvantages.
For example, in the DCO shown in FIG. 15, a wide range of the oscillation frequency can be taken, but since the path of the signals is dynamically switched, when the value of any bit of the count value S.sub.C changes, there is a danger that the signal will be momentarily interrupted, so there is a problem in continuity of the signal.
Further, during operation, the circuit as a whole is not stable in state. Jitter occurs due to the switching (change) of the value of the control signal.
Further, in the DCO shown in FIG. 16, the frequency transition of the oscillation signal is continuous and smooth, but the currents of the delay elements are considerably affected by the resistances of the drive use transistors Tp.sub.00 and Tn.sub.00, so there is a problem that a wide oscillation frequency range cannot be obtained.
In order to obtain a wide oscillation frequency range in the DCO shown in FIG. 16, it is necessary to make the resistances of the drive use transistors Tp.sub.00 and Tn.sub.00 small, that is, make the sizes of the transistors large. This consequently induces an increase of power consumption of the delay elements. Further, where transistors are actually formed on a substrate, there is a limit to the size of the transistors.
Further, during operation, the circuit as a whole is not stable in state. Jitter occurs due to the switching (change) of the value of the control signal.